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1 LT1737 high power isolated flyback controller november 2000 the lt ? 1737 is a monolithic switching regulator control- ler specifically designed for the isolated flyback topology. it drives the gate of an external mosfet and is generally powered from a dc supply voltage. output voltage feed- back information may be supplied by a variety of methods including a third transformer winding, the primary wind- ing or even direct dc feedback (see applications informa- tion). its gate drive capability coupled with a suitable external mosfet and other power path components can deliver load power up to tens of watts. the LT1737 has a number of features not found on other isolated flyback controller ics presently available. by utilizing current mode switching techniques, it provides excellent ac and dc line regulation. its unique control circuitry can maintain regulation well into discontinuous mode in most applications. optional load compensation circuitry allows for improved load regulation. an optional undervoltage lockout pin halts operation when the appli- cation input voltage is too low. an optional external capacitor implements a soft-start function. n drives external power mosfet with external i sense resistor n supply voltage range: 4.5v to 20v n flyback voltage limited only by external components n senses output voltage directly from primary side windingno optoisolator required n moderate accuracy regulation without user trims n regulation maintained well into discontinuous mode n switching frequency from 50khz to 250khz with external capacitor n available in 16-pin gn and so packages n optional load compensation n optional undervoltage lockout n shdn pin reduces i q to 50 m a typ , ltc and lt are registered trademarks of linear technology corporation. n isolated flyback switching regulators n medical instruments n instrumentation power supplies information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. final electrical specifications features descriptio u applicatio s u 12v-18v to isolated 15v converter si plified sche atic ww pgnd i sense gate v c fb r1 0.27 m1 irfl014 t1 coiltronics ctx150-4 v in v cc uvlo sgnd 1737 ta01 r cmpc r ocmp minenab LT1737 endly oscap t on r3 3.01k 1% c3 0.1 f d1 mbrs1100 c2 33 f + r4 7.5k v out d2 bas16 q1 2n3906 r2 35.7k 1% c1 22 f 150 h 150 h +
2 LT1737 (note 1) v cc supply voltage ................................................. 22v uvlo pin voltage .................................................... v cc i sense pin voltage .................................................... 2v fb pin current ..................................................... 2ma operating junction temperature range LT1737c .............................................. 0 c to 100 c LT1737i ........................................... C 40 c to 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................ 300 c order part number LT1737cgn LT1737cs LT1737ign LT1737is t jmax = 125 c, q ja = 110 c/w (gn) t jmax = 125 c, q ja = 100 c/w (so) package/order i for atio uu w absolute axi u rati gs w ww u top view s package 16-lead plastic so gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 pgnd i sense sfst r ocmp r cmpc oscap v c fb gate v cc t on endly minenab sgnd uvlo 3v out the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 14v, gate open, v c = 1.4v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units power supply v cc(min) minimum input voltage l 4.1 4.5 v i cc supply current l 10 15 ma shutdown current v uvlo = 0v, v c = open l 50 150 m a feedback amplifier v fb feedback voltage 1.230 1.245 1.260 v l 1.220 1.270 v i fb feedback pin input current 500 na g m feedback amplifier transconductance d l c = 10 m a l 400 1000 1800 m mho i src , i snk feedback amplifier source or sink current l 30 50 80 m a v cl feedback amplifier clamp voltage 2.5 v reference voltage/current line regulation 4.75v v in 18v l 0.01 0.05 %/v voltage gain v c = 1v to 2v 2000 v/v soft-start charging current v sfst = 0v 25 40 50 m a soft-start discharge current v sfst = 1.5v, v uvlo = 0v 0.8 1.5 ma gate output v gate output high level i gate = 100ma l 11.5 12.1 v i gate = 500ma l 11.0 11.8 v output low level i gate = 100ma l 0.3 0.45 v i gate = 500ma l 0.6 1.0 v i gate output sink current in shutdown, v uvlo = 0v v gate = 2v l 1.2 2.5 ma t r rise time c l = 1000pf 30 ns t f fall time c l = 1000pf 30 ns gn part marking 1737 1737i consult factory for parts specified with wider operating temperature ranges.
3 LT1737 note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: component value range guaranteed by design. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 14v, gate open, v c = 1.4v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units current amplifier v c control pin threshold duty cycle = min 0.90 1.12 1.25 v l 0.80 1.35 v v isense switch current limit duty cycle 30% 220 250 270 mv duty cycle 30% l 200 280 mv duty cycle = 80% 220 mv d v isense / d v c 0.30 mv timing f switching frequency c oscap = 100pf 90 100 115 khz l 80 125 khz c oscap oscillator capacitor value (note 2) 33 200 pf t on minimum switch on time r ton = 50k 200 ns t ed flyback enable delay time r endly = 50k 200 ns t en minimum flyback enable time r menab = 50k 200 ns r t timing resistor value (note 2) 24 240 k w maximum switch duty cycle l 85 90 % load compensation sense offset voltage 25mv current gain factor 0.80 0.95 1.05 mv uvlo function v uvlo uvlo pin lockout threshold l 1.21 1.25 1.29 v uvlo pin shutdown threshold 0.75 v l 0.4 0.95 v i uvlo uvlo pin bias current v uvlo = 1.2v C 0.25 + 0.1 + 0.25 m a v uvlo = 1.3v C 4.50 C 3.5 C 2.50 m a 3v output function v ref reference output voltage i load = 1ma l 2.8 3.0 3.2 v output impedance 10 w current limit l 815 ma uu u pi fu ctio s pgnd (pin 1): the power ground pin carries the gate node discharge current. this is typically a current spike of several hundred ma with a duration of tens of nanosec- onds. it should be connected directly to a good quality ground plane. i sense (pin 2): pin to measure switch current with external sense resistor. the sense resistor should be of a nonin- ductive construction as high speed performance is essen- tial. proper grounding technique is also required to avoid distortion of the high speed current waveform. a preset internal limit of nominally 250mv at this pin effects a switch current limit.
4 LT1737 uu u pi fu ctio s sfst (pin 3): pin for optional external capacitor to effect soft-start function. see applications information for details. r ocmp (pin 4): input pin for optional external load com- pensation resistor. use of this pin allows nominal com- pensation for nonzero output impedance in the power transformer secondary circuit, including secondary wind- ing impedance, output schottky diode impedance and output capacitor esr. in less demanding applications, this resistor is not needed. see applications information for more details. r cmpc (pin 5): pin for external filter capacitor for optional load compensation function. a common 0.1 m f ceramic capacitor will suffice for most applications. see applica- tions information for further details. oscap (pin 6): pin for external timing capacitor to set oscillator switching frequency. see applications informa- tion for details. v c (pin 7): this is the control voltage pin which is the output of the feedback amplifier and the input of the current comparator. frequency compensation of the overall loop is effected in most cases by placing a capacitor between this node and ground. fb (pin 8): input pin for external feedback resistor divider. the ratio of this divider, times the internal band- gap (v bg ) reference, times the effective transformer turns ratio is the primary determinant of the output voltage. the thevenin equivalent resistance of the feedback divider should be roughly 3k. see applications information for more details. 3v out (pin 9): output pin for nominal 3v reference. this facilitates various user applications. this node is internally current limited for protection and is intended to drive either moderate capacitive loads of several hundred pf or less, or, very large capacitive loads of 0.1 m f or more. see applications information for more details. uvlo (pin 10): this is a dual function pin that implements both undervoltage lockout and shutdown functions. pull- ing this pin to near ground effects shutdown and reduces quiescent current to tens of microamperes. additionally, an external resistor divider between v in and ground may be connected to this pin to implement an undervoltage lockout function. the bias current on this pin is a function of the state of the uvlo comparator; as the threshold is exceeded, the bias current increases. this creates a hysteresis band equal to the change in bias current times the thevenin impedance of the users resis- tive divider. the user may thereby adjust the impedance of the uvlo divider to achieve a desired degree of hysteresis. a 100pf capacitor to ground is recommended on this pin. see application information for details. sgnd (pin 11): the signal ground pin is a clean ground. the internal reference, oscillator and feedback amplifier are referred to it. keep the ground path connection to the fb pin, oscap capacitor and the v c compensation capaci- tor free of large ground currents. minenab (pin 12): pin for external programming resistor to set minimum enable time. see applications information for details. endly (pin 13): pin for external programming resistor to set enable delay time. see applications information for details. t on (pin 14): pin for external programming resistor to set switch minimum on time. see applications information for details. v cc (pin 15): supply voltage for the LT1737. bypass this pin to ground with 1 m f or more. gate (pin 16): this is the gate drive to the external power mosfet switch and has large dynamic currents flowing through it. keep the trace to the mosfet as short as possible to minimize electromagnetic radiation and volt- age spikes. a series resistance of 5 w or more may help to dampen ringing in less than ideal layouts.
5 LT1737 block diagra w comp endly minenab t on i amp fdbk fb oscap osc mosfet driver uvlo v cc 3v out 3v reg (internal) bias v c soft-start load compensation i sense gate pgnd r ocmp sfst r cmpc sgnd 1737 bd logic
6 LT1737 ti i g diagra u ww flyback error a plifier w v sw voltage v in gnd off on minimum t on enable delay minimum enable time 1737 td off on switch state flyback amp state 0.80 v flbk v flbk collapse detect enabled disabled disabled + d1 t1 isolated v out c1 m1 + v in v c c2 r2 r1 fb v bg q1 q2 i i m i m i fxd enab 1737 ea
7 LT1737 the LT1737 is a current mode switcher controller ic designed specifically for the isolated flyback topology. the block diagram shows an overall view of the system. many of the blocks are similar to those found in traditional designs, including: internal bias regulator, oscillator, logic, current amplifier and comparator, driver and out- put switch. the novel sections include a special flyback error amplifier and a load compensation mechanism. also, due to the special dynamic requirements of flyback control, the logic system contains additional functionality not found in conventional designs. the LT1737 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier that derives its feedback informa- tion from the flyback pulse. due to space constraints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. a good source of information on these topics is application note an19. error amplifierpseudo dc theory please refer to the simplified diagram of the flyback error amplifier. operation is as follows: when mosfet output switch m1 turns off, its drain voltage rises above the v in rail. the amplitude of this flyback pulse as seen on the third winding is given as: v v v i esr n flbk out f sec st = ++ () v f = d1 forward voltage i sec = transformer secondary current esr = total impedance of secondary circuit n st = transformer effective secondary-to-third winding turns ratio the flyback voltage is then scaled by external resistor divider r1/r2 and presented at the fb pin. this is then compared to the internal bandgap reference by the differ- ential transistor pair q1/q2. the collector current from q1 is mirrored around and subtracted from fixed current source i fxd at the v c pin. an external capacitor integrates this net current to provide the control voltage to set the current mode trip point. operatio u the relatively high gain in the overall loop will then cause the voltage at the fb pin to be nearly equal to the bandgap reference v bg . the relationship between v flbk and v bg may then be expressed as: v rr r v flbk bg = + () 12 2 combination with the previous v flbk expression yields an expression for v out in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: vv rr rn v i esr out bg st fsec = + () ? ? ? ? 12 2 1 additionally, it includes the effect of nonzero secondary output impedance, which is discussed in further detail, see load compensation theory. the practical aspects of applying this equation for v out are found in the applica- tions information section. so far, this has been a pseudo-dc treatment of flyback error amplifier operation. but the flyback signal is a pulse, not a dc level. provision must be made to enable the flyback amplifier only when the flyback pulse is present. this is accomplished by the dotted line connections to the block labeled enab. timing signals are then required to enable and disable the flyback amplifier. error amplifierdynamic theory there are several timing signals that are required for proper LT1737 operation. please refer to the timing diagram. minimum output switch on time the LT1737 effects output voltage regulation via flyback pulse action. if the output switch is not turned on at all, there will be no flyback pulse and output voltage informa- tion is no longer available. this would cause irregular loop response and start-up/latchup problems. the solution cho- sen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. this in turn estab- lishes a minimum load requirement to maintain regula- tion. see applications information for further details.
8 LT1737 operatio u enable delay when the output switch shuts off, the flyback pulse appears. however, it takes a finite time until the trans- former primary side voltage waveform approximately rep- resents the output voltage. this is partly due to finite rise time on the mosfet drain node, but more importantly, due to transformer leakage inductance. the latter causes a voltage spike on the primary side not directly related to output voltage. (some time is also required for internal settling of the feedback amplifier circuitry.) in order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turnoff command and the enabling of the feedback amplifier. this is termed enable delay. in certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. see application infor- mation for further details. collapse detect once the feedback amplifier is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, which compares the flyback voltage (fb referred) to a fixed reference, nominally 80% of v bg . when the flyback waveform drops below this level, the feedback amplifier is disabled. this action accommodates both continuous and discontinuous mode operation. minimum enable time the feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed minimum enable time. this prevents lockup, especially when the output voltage is abnormally low, e.g., during start-up. the mini- mum enable time period ensures that the v c node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. the minimum enable time often determines the low load level at which output voltage regulation is lost. see applications information for details. effects of variable enable period it should now be clear that the flyback amplifier is enabled during only a portion of the cycle time. this can vary from the fixed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of flyback amp behavior will then be directly affected by the variable enable period. these include effective transconductance and v c node slew rate. load compensation theory the LT1737 uses the flyback pulse to obtain information about the isolated output voltage. a potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, t1 m1 r3 50k v in r2 load comp i r1 fb v bg q1 q2 i m i m r ocmp r cmpc r sense i sense 1737 f01 q3 + a1 figure 1. load compensation diagram
9 LT1737 transformer secondary and output capacitor. this has been represented previously by the expression i sec ? esr. however, it is generally more useful to convert this expression to an effective output impedance. because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the off duty cycle. that is: r esr dc out off = ? ? ? ? 1 where r out = effective supply output impedance esr = lumped secondary impedance dc off = off duty cycle expressing this in terms of the on duty cycle, remember- ing dc off = 1 C dc, r esr dc out = ? ? ? ? 1 1 dc = on duty cycle in less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external fb resistor divider adjusted to compensate for nominal expected error. in more demanding applications, output impedance error may be minimized by the use of the load compensa- tion function. to implement the load compensation function, a voltage is developed that is proportional to average output switch current. this voltage is then impressed across the external r ocmp resistor, and the resulting current acts to decrease the voltage at the fb pin. as output loading increases, average switch current increases to maintain rough output voltage regulation. this causes an increase in r ocmp resistor current which effects a corresponding increase in flyback voltage amplitude. assuming a relatively fixed power supply efficiency, eff, power out = eff ? power in v out ? i out = eff ? v in ? i in average primary side current may be expressed in terms of output current as follows: operatio u i v v eff i in out in out = ? ? ? ? combining the efficiency and voltage terms in a single variable: i in = k1 ? i out , where k v v eff out in 1 = ? ? ? ? switch current is converted to voltage by the external sense resistor and averaged/lowpass filtered by r3 and the external capacitor on r cmpc . this voltage is then impressed across the external r ocmp resistor by op amp a1 and transistor q3. this produces a current at the collector of q3 which is then mirrored around and then subtracted from the fb node. this action effectively in- creases the voltage required at the top of the r1/r2 feedback divider to achieve equilibrium. so the effective change in v out target is: d=d () ? ? ? ? d d = ? ? ? ? vki r r rror v i k r r rr out out sense ocmp out out sense ocmp 112 112 (||) ( || ) nominal output impedance cancellation is obtained by equating this expression with r out : rk r r r r and rk r r r r where out sense ocmp ocmp sense out = ? ? ? ? = ? ? ? ? 112 112 ( || ) ( || ) k1 = dimensionless variable related to v in , v out and efficiency as above r sense = external sense resistor r out = uncompensated output impedance (r1||r2) = impedance of r1 and r2 in parallel the practical aspects of applying this equation to deter- mine an appropriate value for the r ocmp resistor are found in the applications information section.
10 LT1737 applicatio s i for atio wu uu transformer design considerations transformer specification and design is perhaps the most critical part of applying the LT1737 successfully. in addi- tion to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should prove useful. turns ratios note that due to the use of the external feedback resistor divider ratio to set output voltage, the user has relative freedom in selecting transformer turns ratio to suit a given application. in other words, screwball turns ratios like 1.736:1.0 can scrupulously be avoided! in contrast, simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting total turns and mutual inductance. turns ratio can then be chosen on the basis of desired duty cycle. however, remember that the input supply voltage plus the second- ary-to-primary referred version of the flyback pulse (in- cluding leakage spike) must not exceed the allowed external mosfet breakdown rating. leakage inductance transformer leakage inductance (on either the primary or secondary) causes a spike after output switch turnoff. this is increasingly prominent at higher load currents, where more stored energy must be dissipated. in many cases a snubber circuit will be required to avoid overvoltage breakdown at the output switch node. application note an19 is a good reference on snubber design. in situations where the flyback pulse extends beyond the enable delay time, the output voltage regulation will be affected to some degree. it is important to realize that the feedback system has a deliberately limited input range, roughly 50mv referred to the fb node, and this works to the users advantage in rejecting large, i.e., higher voltage, leakage spikes. in other words, once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. so the user is generally advised to arrange the snubber circuit to clamp at as high a voltage as comfortably possible, observing mosfet breakdown, such that leakage spike duration is as short as possible. as a rough guide, total leakage inductances of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to perhaps ten percent cause increasing regulation error. severe leakage inductances in the double digit percentage range should be avoided if at all possible as there is a potential for abrupt loss of control at high load current. this curious condition potentially occurs when the leak- age spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this will typically reduce the output volt- age abruptly to a fraction, perhaps between one-third to two-thirds of its correct value. if load current is reduced sufficiently, the system will snap back to normal opera- tion. when using transformers with considerable leakage inductance, it is important to exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at an abnormally low value, the system has a problem. this will usually be evident by simultaneously monitoring the v sw waveform on an oscilloscope to observe leakage spike behavior firsthand. a final notethe susceptibility of the system to bistable behavior is somewhat a function of the load i/v characteristics. a load with resistive, i.e., i = v/r behavior is the most susceptible to bistability. loads which exhibit cmossy, i.e., i = v 2 /r behavior are less susceptible. secondary leakage inductance in addition to the previously described effects of leakage inductance in general, leakage inductance on the second- ary in particular exhibits an additional phenomenon. it forms an inductive divider on the transformer secondary,
11 LT1737 applicatio s i for atio wu uu which reduces the size of the primary-referred flyback pulse used for feedback. this will increase the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomena is load indepen- dent. to the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the feedback resistor divider ratio. winding resistance effects resistance in either the primary or secondary will act to reduce overall efficiency (p out /p in ). resistance in the secondary increases effective output impedance which degrades load regulation, (at least before load compensa- tion is employed). bifilar winding a bifilar or similar winding technique is a good way to minimize troublesome leakage inductances. however, re- member that this will increase primary-to-secondary ca- pacitance and limit the primary-to-secondary breakdown voltage, so bifilar winding is not always practical. finally, the ltc applications group is available to assist in the choice and/or design of the transformer. happy winding! selecting feedback resistor divider values the expression for v out developed in the operation sec- tion can be rearranged to yield the following expression for the r1/r2 ratio: rr r v v i esr v n out f sec bg st 12 2 + () = ++ () where: v out = desired output voltage v f = switching diode forward voltage i sec ? esr = secondary resistive losses v bg = data sheet reference voltage value n st = effective secondary-to-third winding turns ratio the above equation defines only the ratio of r1 to r2, not their individual values. however, a second equation for two unknowns is obtained from noting that the thevenin impedance of the resistor divider should be roughly 3k for bias current cancellation and other reasons. selecting r ocmp resistor value the operation section previously derived the following expressions for r out , i.e., effective output impedance and r ocmp , the external resistor value required for its nominal compensation: r esr dc rk r r rr out ocmp sense out = ? ? ? ? = ? ? ? ? () 1 1 112 || while the value for r ocmp may therefore be theoretically determined, it is usually better in practice to employ empirical methods. this is because several of the required input variables are difficult to estimate precisely. for instance, the esr term above includes that of the trans- former secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resis- tance. similarly, k1 appears to be a simple ratio of v in to v out times (differential) efficiency, but theoretically esti- mating efficiency is not a simple calculation. the sug- gested empirical method is as follows: build a prototype of the desired supply using the eventual secondary components. temporarily ground the r cmpc pin to disable the load compensation function. operate the supply over the expected range of output current loading while measuring the output voltage deviation. approxi- mate this variation as a single value of r out (straight line approximation). calculate a value for the k1 constant based on v in , v out and the measured (differential) effi- ciency. these are then combined with r sense as indicated to yield a value for r ocmp . verify this result by connecting a resistor of roughly this value from the r ocmp pin to ground. (disconnect the ground short to r cmpc and connect the requisite 0.1 m f filter capacitor to ground.) measure the output impedance with the new compensation in place. modify the original r ocmp value if necessary to increase or decrease the effective compensation.
12 LT1737 selecting oscillator capacitor value the switching frequency of the LT1737 is set by an external capacitor connected between the oscap pin and ground. recommended values are between 200pf and 33pf, yielding switching frequencies between 50khz and 250khz. figure 2 shows the nominal relationship between external capacitance and switching frequency. to mini- mize stray capacitance and potential noise pickup, this capacitor should be placed as close as possible to the ic and the oscap node length/area minimized. applicatio s i for atio wu uu indicative of actual current level in the transformer pri- mary, and may cause irregular current mode switching action, especially at light load. however, the user must remember that the LT1737 does not skip cycles at light loads. therefore, minimum on time will set a limit on minimum delivered power and con- sequently a minimum load requirement to maintain regu- lation (see minimum load considerations). similarly, minimum on time has a direct effect on short-circuit be- havior (see maximum load/short-circuit considerations). the user is normally tempted to set the minimum on time to be short to minimize these load related consequences. (after all, a smaller minimum on time approaches the ideal case of zero, or no minimum.) however, a longer time may be required in certain applications based on mosfet switching current spike considerations. enable delay time this function provides a programmed delay between turnoff of the gate drive node and the subsequent enabling of the feedback amplifier. at high loads, a primary side voltage spike after mosfet turnoff may be observed due to transformer leakage inductance. this spike is not in- dicative of actual output voltage (see figure 4b). delaying the enabling of the feedback amplifier allows this system to effectively ignore most or all of the voltage spike and maintain proper output voltage regulation. the enable delay time should therefore be set to the maximum ex- pected duration of the leakage spike. this may have c oscap (pf) 30 50 f osc (hz) 100 300 100 200 1737 f02 figure 2. f osc vs oscap value selecting timing resistor values there are three internal one-shot times that are pro- grammed by external application resistors: minimum on time, enable delay time and minimum enable time. these are all part of the isolated flyback control technique, and their functions have been previously outlined in the opera- tion section. figure 3 shows nominal observed time ver- sus external resistor value for these functions. the following information should help in selecting and/or optimizing these timing values. minimum on time this time defines a period whereby the normal switch current limit is ignored. this feature provides immunity to the leading edge current spike often seen at the source node of the external power mosfet, due to rapid charging of its gate/source capacitance. this current spike is not r t (k ) 20 100 500 time (ns) 1000 100 250 1737 f03 figure 3. one shot times vs programming resistor
13 LT1737 implications regarding output voltage regulation at mini- mum load (see minimum load considerations). a second benefit of the enable delay time function occurs at light load. under such conditions the amount of energy stored in the transformer is small. the flyback waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage (see figure 4c). so the enable delay time should also be set long enough to ignore the irrelevant portion of the flyback waveform at light load. additionally, there are cases wherein the gate output is called upon to drive a large geometry mosfet such that the turnoff transition is slowed significantly. under such circumstances, the enable delay time may be increased to accommodate for the lengthy transition. average start-up v c current = minimum enable time switching frequency i src minimum enable time can also have implications at light load (see minimum load considerations). the temptation is to set the minimum enable time to be fairly short, as this is the least restrictive in terms of minimum load behavior. however, to provide a reliable minimum start-up current of say, nominally 1 m a, the user should set the minimum enable time at no less that 2% of the switching period (= 1/switching frequency). current sense resistor considerations the external current sense resistor allows the user to optimize the current limit behavior for the particular appli- cation under consideration. as the current sense resistor is varied from several ohms down to tens of milliohms, peak switch current goes from a fraction of an ampere to tens of amperes. care must be taken to ensure proper circuit operation, especially with small current sense resistor values. for example, a peak switch current of 10a requires a sense resistor of 0.025 w . note that the instantaneous peak power in the sense resistor is 2.5w, and it must be rated accordingly. the LT1737 has only a single sense line to this resistor. therefore, any parasitic resistance in the ground side connection of the sense resistor will increase its apparent value. in the case of a 0.025 w sense resistor, one milliohm of parasitic resistance will cause a 4% reduction in peak switch current. so resistance of printed circuit copper traces and vias cannot necessarily be ignored. an additional consideration is parasitic inductance. in- ductance in series with the current sense resistor will accentuate the high frequency components of the current waveform. in particular, the gate switching spike and multimegahertz ringing at the mosfet can be considerably amplified. if severe enough, this can cause erratic operation. for example, assume 3nh of parasitic inductance (equivalent to about 0.1 inch of wire in free space) is in series with an ideal 0.025 w sense resistor. a zero will be formed at f = r/(2 p l), or 1.3mhz. above applicatio s i for atio wu uu enable delay time needed 1737 f04 discontinuous mode ringing idealized flyback waveform mosfet gate drive flyback waveform with large leakage spike at heavy load ?low?flyback waveform at light load b a c enable delay time needed figure 4 minimum enable time this function sets a minimum duration for the expected flyback pulse. its primary purpose is to provide a mini- mum source current at the v c node to avoid start-up problems.
14 LT1737 this frequency the sense resistor will behave like an inductor. several techniques can be used to tame this potential parasitic inductance problem. first, any resistor used for current sensing purposes must be of an inherently non- inductive construction. mounting this resistor directly above an unbroken ground plane and minimizing its ground side connection will serve to absolutely minimize parasitic inductance. in the case of low valued sense resistors, these may be implemented as a parallel combi- nation of several resistors for the thermal considerations cited above. the parallel combination will help to lower the parasitic inductance. finally, it may be necessary to place a pole between the current sense resistor and the LT1737 i sense pin to undo the action of the inductive zero (see figure 5). a value of 51 w is suggested for the resistor, while the capacitor is selected empirically for the particular application and layout. using good high frequency mea- surement techniques, the i sense pin waveform may be observed directly with an oscilloscope while the capacitor value is varied. applicatio s i for atio wu uu gate parasitic inductance c comp r sense l p 1737 f05 51 pgnd sgnd i sense f = r sense 2 l p sense resistor zero at: f = 1 2 (51 )c comp compensating pole at: c comp = l p r sense (51 ) for cancellation: figure 5 soft-start function the LT1737 contains an optional soft-start function that is enabled by connecting an explicit external capacitor be- tween the sfst pin and ground. internal circuitry prevents the control voltage at the v c pin from exceeding that on the sfst pin. th e soft-start function is enagaged whenever v cc power is removed, or as a result of either undervoltage lockout or thermal (overtemperature) shutdown. the sfst node is then discharged rapidly to roughly a v be above ground. (remember that the v c pin control node switching threshold is deliberately set at a v be plus several hundred millivolts.) when this condition is removed, a nominal 40 m a current acts to charge up the sfst node towards roughly 3v. so, for example, a 0.1 m f soft-start capacitor will place a 0.4v/ms limit on the ramp rate at the v c node. uvlo pin function the uvlo pin effects both undervoltage lockout and shutdown functions. this is accomplished by using differ- ent voltage thresholds for the two functionsthe shut- down function is at roughly a v be above ground (0.75v at 25 c, large temperature variation), while the uvlo func- tion is at nearly a bandgap voltage (1.25v, fairly stable with temperature). an external resistor divider between the input supply and ground can then be used to achieve a user-programmable undervoltage lockout (see figure 6a). an additional feature of this pin is that there is a change in the input bias current at this pin as a function of the state of the internal uvlo comparator. as the pin is brought above the uvlo threshold, the bias current sourced by the part increases. this positive feedback effects a hysteresis band for reliable switching action. note that the size of the hysteresis is proportional to the thevenin impedance of the external uvlo resistor divider network, which makes it user programmable. as a rough rule of thumb, each 4k or so of impedance generates about 1% of hysteresis. (this is based on roughly 1.25v for the threshold and 3 m a for the bias current shift.) even in good quality ground plane layouts, it is common for the switching node (mosfet drain) to couple to the uvlo pin with a stray capacitance of several thousandths of a pf. to ensure proper uvlo action, a 100pf capacitor is recommended from this pin to ground as shown in figure 6b. this will typically reduce the coupled noise to a few millivolts. the uvlo filter capacitor should not be made much larger than a few hundred pf, however, as the hysteresis action will become too slow. in cases where further filtering is required, e.g., to attenuate high speed supply ripple, the topology in figure 6c is recommended. resistor r1 has been split into two equal parts. this provides a node for effecting capacitor filtering of high speed supply ripple, while leaving the uvlo pin node impedance relatively unchanged at high frequency.
15 LT1737 v in uvlo r1 r2 v in uvlo r1 r2 c1 100pf v in uvlo r1/2 r1/2 r2 1737 f06 c2 c1 100pf applicatio s i for atio wu uu figure 6 frequency compensation loop frequency compensation is performed by connect- ing a capacitor from the output of the error amplifier (v c pin) to ground. an additional series resistor, often re- quired in traditional current mode switcher controllers, is usually not required and can even prove detrimental. the phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a zero to the loop response. in further contrast to traditional current mode switchers, v c pin ripple is generally not an issue with the LT1737. the dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the v c voltage changes during the flyback pulse, but is then held during the subsequent switch on portion of the next cycle. this action naturally holds the v c voltage stable during the current comparator sense action (current mode switching). output voltage error sources conventional nonisolated switching power supply ics typically have only two substantial sources of output voltage error: the internal or external resistor divider network that connects to v out and the internal ic refer- ence. the LT1737, which senses the output voltage in both a dynamic and an isolated manner, exhibits additional potential error sources to contend with. some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. here is a list of possible error sources and their effective contribution. internal voltage reference the internal bandgap voltage reference is, of course, imperfect. its error, both at 25 c and over temperature is already included in the specifications. user programming resistors output voltage is controlled by the user-supplied feedback resistor divider ratio. to the extent that the resistor ratio differs from the ideal value, the output voltage will be proportionally affected. highest accuracy systems will demand 1% components. schottky diode drop the LT1737 senses the output voltage from the trans- former primary side during the flyback portion of the cycle. this sensed voltage therefore includes the forward drop, v f , of the rectifier (usually a schottky diode). the nominal v f of this diode should therefore be included in feedback resistor divider calculations. lot to lot and ambient temperature variations will show up as output voltage shift/drift. secondary leakage inductance leakage inductance on the transformer secondary re- duces the effective secondary-to-third winding turns ratio (n s /n t ) from its ideal value. this will increase the output voltage target by a similar percentage. to the extent that secondary leakage inductance is constant from part to part, this can be accommodated by adjusting the feedback resistor ratio. (6c) recommended topology to filter high frequency ripple (6b) filter capacitor directly on uvlo note (6a) standard uvlo divider topology
16 LT1737 output impedance error an additional error source is caused by transformer sec- ondary current flow through the real life nonzero imped- ances of the output rectifier, transformer secondary and output capacitor. because the secondary current only flows during the off portion of the duty cycle, the effective output impedance equals the dc lumped secondary impedance times the inverse of the off duty cycle. if the output load current remains relatively constant, or, in less critical applications, the error may be judged acceptable and the feedback resistor divider ratio adjusted for nomi- nal expected error. in more demanding applications, out- put impedance error may be minimized by the use of the load compensation function (see load compensation). minimum load considerations the LT1737 generally provides better low load perfor- mance than previous generation switcher/controllers uti- lizing indirect output voltage sensing techniques. specifically, it contains circuitry to detect flyback pulse collapse, thereby supporting operation well into discon- tinuous mode. nevertheless, there still remain constraints to ultimate low load operation. these relate to the mini- mum switch on time and the minimum enable time. discontinuous mode operation will be assumed in the following theoretical derivations. as outlined in the operation section, the LT1737 utilizes a minimum output switch on time, t on . this value can be combined with expected v in and switching frequency to yield an expression for minimum delivered power. minimum power f l vt vi pri in on out out = ? ? ? ? () = 1 2 2 this expression then yields a minimum output current constraint: i f lv vt out min pri out in on () = ? ? ? ? () 1 2 2 where f = switching frequency l pri = transformer primary side inductance v in = input voltage v out = output voltage t on = output switch minimum on time an additional constraint has to do with the minimum enable time. the LT1737 derives its output voltage infor- mation from the flyback pulse. if the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. the onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, t ed , plus the minimum enable time, t en . minimum power delivered to the load is then: minimum power f l vtt vi sec out en ed out out = ? ? ? ? + () [] = 1 2 2 which yields a minimum output constraint: i fv l tt out min out sec ed en () = ? ? ? ? + () 1 2 2 where f = switching frequency l sec = transformer secondary side inductance v out = output voltage t ed = enable delay time t en = minimum enable time note that generally, depending on the particulars of input and output voltages and transformer inductance, one of the above constraints will prove more restrictive. in other words, the minimum load current in a particular applica- tion will be either output switch minimum on time constrained, or minimum flyback pulse time constrained. (a final notel pri and l sec refer to transformer induc- tance as seen from the primary or secondary side respec- tively. this general treatment allows these expressions to be used when the transformer turns ratio is nonunity.) applicatio s i for atio wu uu
17 LT1737 maximum load/short-circuit considerations the LT1737 is a current mode controller. it uses the v c node voltage as an input to a current comparator that turns off the output switch on a cycle-by-cycle basis as this peak current is reached. the internal clamp on the v c node, nominally 2.5v, then acts as an output switch peak current limit. this 2.5v at the v c pin corresponds to a value of 250mv at the i sense pin, when the (on) switch duty cycle is less than 40%. for a duty cycle above 40%, the internal slope compensation mechanism lowers the effective i sense voltage limit. for example, at a duty cycle of 80%, the nominal i sense voltage limit is 220mv. this action be- comes the switch current limit specification. maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. overcurrent conditions are handled by the same mecha- nism. the output switch turns on, the peak current is quickly reached and the switch is turned off. because the output switch is only on for a small fraction of the available period, power dissipation is controlled. loss of current limit is possible under certain conditions. remember that the LT1737 normally exhibits a minimum switch on time, irrespective of current trip point. if the duty cycle exhibited by this minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current will not be controlled at the nominal value, and will cycle-by-cycle ratchet up to some higher level. expressed mathemati- cally, the requirement to maintain short-circuit control is: tf vi r vn on f sc sec in sp < + () where t on = output switch minimum on time f = switching frequency i sc = short-circuit output current v f = output diode forward voltage at i sc r sec = resistance of transformer secondary v in = input voltage n sp = secondary-to-primary turns ratio (n sec /n pri ) trouble is typically only encountered in applications with a relatively high product of input voltage times secondary- to-primary turns ratio and/or a relatively long minimum switch on time. (additionally, several real world effects such as transformer leakage inductance, ac winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate.) thermal considerations care should be taken to ensure that the worst-case input voltage condition does not cause excessive die tempera- tures. the 16-lead so package is rated at 100 c/w, and the 16-lead gn at 110 c/w. average supply current is simply the sum of quiescent current given in the specifications section plus gate drive current. gate drive current can be computed as: i g = f ? q g where q g = total gate charge f = switching frequency (note: total gate charge is more complicated than c gs ? v g as it is frequently dominated by miller effect of the c gd . furthermore, both capacitances are nonlinear in practice. fortunately, most mosfet data sheets provide figures and graphs which yield the total gate charge directly per operating conditions.) nearly all gate drive power is dissi- pated in the ic, except for a small amount in the external gate series resistor, so total ic dissipation may be com- puted as: p d(total) = v cc (i q + ? f ? q g ), where i q = quiescent current (from specifications) q g = total gate charge f = switching frequency v cc = LT1737 supply voltage applicatio s i for atio wu uu
18 LT1737 applicatio s i for atio wu uu switch node considerations for maximum efficiency, gate drive rise and fall times are made as short as practical. to prevent radiation and high frequency resonance problems, proper layout of the components connected to the ic is essential, especially the power paths (primary and secondary). b field (mag- netic) radiation is minimized by keeping mosfet leads, output diode and output bypass capacitor leads as short as possible. e field radiation is kept low by minimizing the length and area of all similar traces. a ground plane should always be used under the switcher circuitry to prevent interplane coupling. the high speed switching current paths are shown sche- matically in figure 7. minimum lead length in these paths are essential to ensure clean switching and minimal emi. the path containing the input capacitor, transformer pri- mary and mosfet, and the path containing the trans- former secondary, output diode and output capacitor contain nanosecond rise and fall times. keep these paths as short as possible. gate drive resistor considerations the gate drive circuitry internal to the LT1737 has been designed to have as low an output impedance as practi- cally possibleonly a few ohms. a strong l/c resonance is potentially presented by the inductance of the path leading to the gate of the power mosfet and its overall gate capacitance. for this reason the path from the gate package pin to the physical mosfet gate should be kept as short as possible, and good layout/ground plane prac- tice used to minimize the parasitic inductance. an explicit series gate drive resistor may be useful in some applications to damp out this potential l/c resonance (typically tens of mhz). a minimum value of perhaps several ohms is suggested, and higher values (typically a few tens of ohms) will offer increased damping. however, as this resistor value becomes too large, gate voltage rise time will increase to unacceptable levels, and efficiency will suffer due to the sluggish switching action. figure 7. high speed current switching paths + + pgnd gate 1737 f07 gate discharge path gate charge path primary power path secondary power path v cc v cc v in +
19 LT1737 typical applicatio s u basic application with 3-winding transformer figure 8 shows a compact, low power application of the LT1737. transformer t1 is an off-the-shelf versa-pac tm , #vp1-0190, produced by coiltronics. as manufactured, it consists of six ideally identical independent windings. in this application, two windings are stacked in series on the primary side and three are placed in parallel on the secondary side. this arrangement provides a 2:1 primary- to-secondary turns ratio while maximizing overall effi- ciency. the remaining primary side winding provides a ground-referred version of the flyback voltage waveform for the purpose of feedback. the design accepts an input voltage in the range of 8v to 25v and outputs an isolated 5v. to prevent overvoltage on the LT1737 and the gate of mosfet m1, an lt1121 low dropout linear regulator is employed (u2). resistor di- vider r11/r12 sets the output of u2 at nominally 8.25v. (a few hundred millivolts of dropout will therefore be seen at the very bottom of the input supply range.) the positive going drive potential at the LT1737 gate pin is typically 2v or so below its v cc supply pin, so a logic level mosfet has been specified for m1. capacitor c6 sets the switching frequency at approxi- mately 200khz. optimal load compensation for the trans former and secondary circuit components is set by resistor r8. resistor r10 provides a guaranteed mini- mum load of about 20ma to maintain rough output voltage regulation. the soft-start and uvlo features are unused as shown. pgnd i sense gate v c fb r1 0.2 0.5w irc type lr 2010 m1 irll014 r2 5.1 5% 1 10 7 3 t1 coiltronics vp1-0190 6 4 2 5 r13 51 5% v cc uvlo 3v out sgnd 1737 f08 r cmpc r ocmp minenab LT1737 r7 51k 5% r6 51k 5% c6 47pf 50v npo 6 8 7 3 910 15 16 2 1 2 8 3 14 13 12 4 5 11 1 endly sfst oscap t on c5 1nf 25v x7r r8 4.3k 5% r9 68 5% d2 1n5250 d3 mbr0540 r5 51k 5% r11 24k 5% c1: sanyo aluminum electrolytic (35cv331gx) c2: sanyo poscap (10tpc68m) c8: sanyo poscap (10tpa33m) d1: motorola 30v, 3a schottky rectifier d2: 20v, 500mw zener diode d3: motorola 40v, 0.5a schottky rectifier r12 20k 5% r4 3.92k 1% r3 12.7k 1% c3 1 f 25v z5u c1 330 f 35v v in c7 0.1 f 25v z5u c9 1nf 25v x7r c4 470pf 50v x7r out u2 lt1121 adj inp gnd 11 8 12 d1 mbrd330 9 + c2 68 f 10v + c8 33 f 10v l1 1 h optional output filter + r10 240 5% v out 5v v out 5v l1: coilcraft do1608c-102 1 h, 0.05 inductor m1: int? rectifier irll014 60v, 0.2 logic level n-ch mosfet u2: linear technology micropower ldo regulator figure 8. 8v-25v to isolated 5v converter versa-pac is a trademark of coiltronics, inc.
20 LT1737 typical applicatio s u overall power supply efficiency and output regulation versus input voltage and load current may be seen in figures 9 and 10. available output current is a function of input voltage, varying from 650ma with 8v input to 1100ma with 25v input. in cases when the output switching noise is objectionable, the optional output l/c filter shown may be added. the oscilloscope photos in figure 11 show the dramatic reduc- tion in output voltage ripple with the optional filter. note: it is theoretically possible to extend the input voltage range of this topology higher by raising the breakdown voltage ratings on q1, u2 and m1, while adjusting the transformer windings as necessary. however this ap- proach is generally undesirable as the relatively fixed supply current required by the LT1737 generates more and more wasted heat in linear regulator u2 as input voltage is increased. the lt1725, a close cousin of the LT1737 is recommended in such instances. the lt1725 is very similar to the LT1737, but it contains an integral wide hysteresis undervoltage lockout (uvlo) circuit that monitors the v cc voltage. when used in conjunction with a 3-winding transformer to provide both device power and output voltage feedback information, this allows for a trickle charge start-up from an input voltage of up to hundreds of volts. the lt1725 is thus well suited to operate from telecom input voltages of 48v to 72v, or even offline inputs up to several hundred volts! see the lt1725 data sheet for further information. i load (a) 20 50 40 30 90 80 70 60 1737 f09 efficiency (%) 0.01 1 0.1 v in = 8v v in = 15v v in = 25v i load (ma) 0 output voltage (v) 5.00 v in = 8v 1000 1737 f10 4.75 250 500 750 1250 5.25 v in = 15v v in = 25v figure 9. efficiency vs i load figure 10. output regulation 50mv/div ac coupled v in = 15v 1 m s/div 1737 f11a i load = 900ma 20mhz bandwidth limited without l/c filter 50mv/div ac coupled v in = 15v 1 m s/div 1737 f11b i load = 900ma 20mhz bandwidth limited with l/c filter figure 11
21 LT1737 typical applicatio s u application with 2-winding transformer the previous application example utilized a 3-winding transformer, the third winding providing only feedback information. additional circuitry may be employed to provide feedback information, thus allowing the trans- former to be reduced to a 2-winding topology. (the cost and size savings associated with the transformer often make this a preferable alternative. furthermore, a variety of manufacturers offer off-the-shelf dual wound magnet- ics which often can be applied as 1:1 transformers.) figure 12 shows an LT1737 configured for operation with a dual wound toroid, the coiltronics #ctx150-4 octa-pac tm . a ground referred version of the flyback voltage waveform is now provided by components q1, r2, pgnd i sense gate v c fb r1 0.27 0.5w irc type lr 2010 m1 irfl014 r10 5.1 5% 13 4 t1 coiltronics ctx150-4 v in 2 v cc uvlo 3v out sgnd 1737 f12 r cmpc r ocmp minenab LT1737 r6 100k 5% r5 150k 5% c5 47pf 50v npo 6 8 7 3 910 15 r9 33k 5% r8 240k 5% 16 2 14 13 12 4 5 11 1 endly sfst oscap t on c3 1nf 25v x7r r7 4.7k 5% r11 100 5% d4 1n5252 d3 mbrs1100 r4 75k 5% c1: avx tps tantalum (tpse226m035r0300) c2: avx tps tantalum (tpse336m025r0200) d1, d3: motorola 100v, 1a schottky diode d2: signal diode d4: 24v, 500mw zener diode r3 3.01k 1% c8 0.1 f 25v z5u c4 0.1 f 25v z5u c6 470pf 50v x7r c7 470pf 50v x7r d1 mbrs1100 c2 33 f 25v + r13 7.5k 5% v out 15v r12 100 5% m1: int? rectifier 60v, 0.2 n-ch mosfet d2 bas16 q1 2n3906 r2 35.7k 1% c1 22 f 35v + figure 12. 12v-18v to isolated 15v converter i load (ma) 1 60 efficiency (%) 70 80 90 10 100 1000 1737 f13 50 40 30 20 v in = 12v v in = 15v v in = 18v figure 13. efficiency vs i load i load (ma) 0 output voltage (v) 15.0 v in = 12v 1737 f14 14.5 100 200 300 15.5 v in = 15v v in = 18v figure 14. load regulation octa-pac is a trademark of coiltronics, inc.
22 LT1737 typical applicatio s u r3 and d2. (diode d2 prevents reverse emitter/base breakdown in q1 when mosfet m1 is in the on state.) the raw flyback voltage at the drain of mosfet m1 minus the v be of q1 is converted to a current by r3 and then back to a voltage at r4. or, stated mathematically: vv v r r fb flbk be = () ? ? ? ? 4 3 resistor r13 provides an initial pre-load to the supply output to improve light load regulation. resistor divider r8/r9 sets the undervoltage lockout threshold at nomi- nally 10.4v for turn-on, with turn-off about 600mv lower. overall power supply efficiency and output regulation versus input voltage and load current may be seen in figures 13 and 14. 5v in application the LT1737 is a bipolar technology ic specified to operate down to a minimum input supply voltage of 4.5v. although its gate pin drives low nearly to ground, its high capability is limited by a headroom requirement of roughly 2v be s. thus when operating at a worst case 4.5v supply, the gate output will only drive up to a nominal 3v or so. fortunately, mosfets are now available with specified performance at this level of gate voltage. the circuit shown in figure 15 provides an isolated 5v output from an input between 4.5v and 5.5v. two si9804 low gate voltage mosfets are paralleled to handle the primary-side currentup to 12a peak. this circuit pro- vides more output power than the previous examples. it pgnd i sense gate v c fb r1 0.02 m1 si9804 10 4 9 t1 coiltronics vp5-0083 v in 3 v cc uvlo 3v out sgnd 1737 f15 r cmpc r ocmp minenab LT1737 r6 51k 5% r5 51k 5% c5 47pf 50v npo 6 8 7 3 910 15 16 2 14 13 12 4 5 11 1 endly sfst oscap t on c3 1nf 25v x7r r7 2.2k 5% r8 10 5% d4 1n5240 d3 mbr0520 r4 75k 5% c1a-b, c2a-b: sanyo poscap (10tpb220m) d1: motorola 35v, 8a schottky diode d2: signal diode d3: motorola 20v, 0.5a schottky diode d4: 10v, 500mw zener diode m1, m2: siliconix/vishay 25v, 0.023 n-ch mosfet r1: 5 0.10 , 1w (irc lr2512) t1: coiltronics transformer r3 3.01k 1% c8 1 f 25v z5u c4 0.1 f 25v z5u c9 1nf 25v x7r r11 51 5% 11 2 12 1 m2 si9804 c6 4.7nf 50v x7r c7 2.2nf 50v x7r 5 8 6 7 d1 mbrd835l c2a 220 f 10v + c2b 220 f 10v + r10 270 5% v out 5v r9 15 5% d2 bas16 q1 2n3906 r2 11.0k 1% c1a 220 f 10v + c1b 220 f 10v + figure 15. 4.5v-5.5v to isolated 5v converter
23 LT1737 therefore requires a physically larger transformer. the larg- est size versa-pac is used, a vp5-0083. three windings are paralleled for both the primary and secondary. overall power supply efficiency and output regulation ver- sus load current at the nominal v in = 5v may be seen in figures 16 and 17. typical applicatio s u nonisolated application while the LT1737 was designed to serve isolated flyback applications, it is useful to note that it is also capable of supporting nonisolated applications. these are performed by providing a continuous pseudo-dc feedback signal to the fb pin. (the part behaves as if the flyback waveform is infinitely long.) figure 18 demonstrates just such a system. a sepic topology is shown whereby a 8v to 16v input is converted to a nonisolated 12v output. a conventional resistive feedback divider, r3/r4 drives the fb pin. (ca- pacitor c7 serves to filter out high frequency ripple in the output voltage.) a combination of an r/c network (r11/ c5) in parallel with a single capacitor (c9) on the v c node provides the required loop compensation. the load com- pensation function is unwanted, so the r ocmp pin is left open and the r cmpc pin is grounded. an lt1121 low dropout regulator is programmed to a nominal 8.25v output by the r12/r13 resistor divider, and this allows the LT1737 to drive m1, a logic level mosfet. minimum on time programming resistor r5 is set to 33k to minimize the required output preload. minimum enable time has no direct effect on steady state operation, but programming resistor r7 has been set to 100k for rapid start-up. enable delay resistor is similarly set to 24k. overall power supply efficiency versus input voltage and load current may be seen in figure 19. because this application example utilizes a nonisolated topology, load regulation is not an issue. it is typically 0.2% (25mv) from no load to full load. other nonisolated switching topologies may be similarly implemented. for example, boost and nonisolated fly- back readily suggest themselves. (a nonisolated flyback topology also can be used to generate a negative output voltage. in this case, the feedback is a dynamic waveform derived from the primary side of the transformer, similar to an isolated LT1737 application.) 0.01 60 efficiency (%) 70 80 90 0.1 1 10 1737 f16 50 40 30 20 i load (a) figure 16. efficiency vs i load i load (a) 0 output voltage (v) 5.00 4 1737 f17 4.75 1 2 3 5.25 figure 17. load regulation
24 LT1737 typical applicatio s u pgnd i sense gate v c fb r1 0.025 m1 irlz34s l1 15 h r2 2.7 5% r10 51 5% v cc uvlo 3v out sgnd 1737 f18 r cmpc r ocmp minenab LT1737 r7 100k 5% r6 24k 5% c6 47pf 50v npo 6 8 7 3 910 15 16 2 1 2 8 3 14 13 12 4 5 11 1 endly sfst oscap t on c5 4.7nf 50v x7r r5 33k 5% r11 22k 5% r12 24k 5% c1: sanyo os-con (20sv150m) c2a-b: tokin y5v (ie226zy5u-c505) c3: sanyo poscap (16tpc33m) d1: motorola 40v, 6a schottky diode r13 20k 5% r4 3.01k 1% r3 26.1k 1% r8 160k 5% r9 33k 5% c4 1 f 25v z5u c1 150 f 20v v in l2 15 h c10 470pf 50v x7r c9 47pf 50v npo c7 47pf 50v npo out u2 lt1121 adj inp gnd d1 mbrd640ct + c3 33 f 16v 4 c2a 22 f 25v c2b 22 f 25v + r14 750 5% v out 12v c8 0.1 f 25v z5u l1, l2: coiltronics up4b-150 inductor m1: int? rectifier irlz34s 60v, 0.05 logic level n-ch mosfet r1: irc 4 0.1 , 1w (lr2512) figure 18. 8v-16v to 12v nonisolated converter 0.01 60 efficiency (%) 70 80 90 0.1 1 10 1737 f19 50 40 30 20 i load (a) v in = 8v v in = 16v v in = 12v figure 19. efficiency vs i load part number description comments lt1424-5 isolated flyback switching regulator v in = 3v to 20v, i q = 7ma lt1424-9 isolated flyback switching regulator v in = 3v to 20v, i q = 7ma lt1425 isolated flyback switching regulator general purpose with external application resistor lt1533 ultralow noise 1a switching regulator v in = 2.7v to 23v, reduced emi and switching harmonics lt1725 general purpose isolated flyback controller suitable for telecom or offline input voltage related parts ? linear technology corporation 2000 sn1737 1737is lt/lcg 1100 4k ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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